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Creators/Authors contains: "She, Xueyuan"

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  1. ; ; (, International Join Conference on Neural Network)
    Accepted Manuscript Full Text Available
  2. ; ; (, Design Automation and Test in Europe)
    Full Text Available 
  3. ; ; ; ; ; ; ; (, IEEE Journal on Exploratory Solid-State Computational Devices and Circuits)
    Full Text Available 
  4. ; ; ; ; ; ; ; (, IEEE journal on exploratory solid-state computational devices and circuits)
    This paper presents a Ferroelectric FET (FeFET) based processing-in-memory (PIM) architecture to accelerate inference of deep neural networks (DNNs). We propose a digital in-memory vector-matrix multiplication (VMM) engine design utilizing the FeFET crossbar to enables bit-parallel computation and eliminate analog-to-digital conversion in prior mixed-signal PIM designs. A dedicated hierarchical network-on-chip (H-NoC) is developed for input broadcasting and on-the-fly partial results processing, reducing the data transmission volume and latency. Simulations in 28nm CMOS technology show 115x and 6.3x higher computing efficiency (GOPs/W) over desktop GPU (Nvidia GTX 1080Ti) and ReRAM based design, respectively. 
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    Accepted Manuscript Full Text Available